The present invention provides techniques for combining volatile and non-volatile programmable logic on an integrated circuit (IC), and more particularly, to techniques for providing an IC that has one section of programmable logic configured by off-chip memory and another section of programmable logic configured by on-chip non-volatile memory.
Large field programmable gate arrays (FPGAs) that contain on-chip volatile memory blocks usually require a considerable amount of time to be configured at power-up, because configuration data is loaded onto the chip from an external memory chip. The external memory chip can be, for example, a serial read only memory (SROM).
Small complex programmable logic device (CPLDs) such as Altera's MAX family of CPLDs contain on-chip non-volatile memory. The configuration data is stored in the on-chip non-volatile memory. The configuration data can be loaded quickly from the on-chip non-volatile memory into the programmable logic at power-up. Non-volatile CPLDs are virtually instant-on at power-up and require no external configuration data. However, making a large FPGA have all non-volatile memory can be prohibitive in terms of area and can limit process selection.
Many large volatile FPGAs have a companion CPLD to orchestrate the power-up and configuration process. The CPLD can also encrypt the configuration data before it is transmitted to the FPGA to prevent the configuration data from being intercepted and copied. However, this technique is more complex, because it makes a large FPGA a three-device solution that includes the FPGA, a SROM, and a CPLD.
Therefore, it would be desirable to provide faster techniques for configuring field programmable gate arrays. It would also be desirable to provide users with ways to adequately secure their designs during the configuration process.